跪求VHDL语言编程 题目：8个彩灯依次循环点亮，每次亮一个。

library ieee;
use ieee.std_logic_1164.all;
entity caideng is
port(clk,reset:in std_logic;
output:out std_logic_vector(7 downto 0));
end entity;
architecture art of caideng is
signal data:std_logic_vector(7 downto 0);
begin
process(clk,reset,data)
begin
if reset='1' then
data<="00000000";
elsif clk'event and clk='1' then
if data="00000000" then
data<="00000001";
else data<=data(6 downto 0)&data(7);
end if;
end if;
output<=data;
end process;
end art;

刚好有一个以前做过的设计，已上传中转站，你提去看看是否合适
File Name:彩灯循环.rar (1.48KB)

等待一下，选择“Click here to Download”

在QuartusII7.0环境下做的