用元件例化语句编写该电路的顶层VHDL程序

ARCHITECTURE structure OF sample IS
SIGANL d,e,f,g: bit;
COMPONENT nand3
PORT (a,b,c: IN bit;
y: OUT bit);

END COMPONENT;
COMPONENT and2
PORT (a,b: IN bit;
y: OUT bit);

END COMPONENT;
COMPONENT nor3
PORT (a,b,c: IN bit;
y: OUT bit);

END COMPONENT;
BEGIN
u0: nand3 PORT MAP (a => a, b => b, c => c, y => d);
u1: and2 PORT MAP (a => a, b => d, y => e);
u2: and2 PORT MAP (a => d, b => b, y => f);
u3: and2 PORT MAP (a => d, b => c, y => g);
u4: nor3 PORT MAP (a => e, b => f, c => g, y => y);
END structure;