用VHDL设计电子时钟

***********百分秒*************************
entity count100 is
Port ( shift_temp,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0);
co:out std_logic);
end count100;

architecture Behavioral of count100 is
signal temp:std_logic_vector(7 downto 0):=(others=>'0');
begin
process(clk)
begin
if clk'event and clk='1' then
if temp(3 downto 0)=9 then
if temp(7 downto 4)=9 then
temp<=(others=>'0');co<='1';
else temp(7 downto 4)<=temp(7 downto 4)+1;temp(3 downto 0)<=(others=>'0');co<='0';end if;
else temp(3 downto 0)<=temp(3 downto 0)+1;co<='0';end if;
end if;
end process;
q<=temp;
end Behavioral;

****************************秒，分*******************
entity count60 is
Port ( shift_temp,key_m,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0);
co:out std_logic);
end entity;
architecture Behavioral of count60 is
signal temp:std_logic_vector(7 downto 0):=(others=>'0');
signal temp_clk,temp_co:std_logic;
begin
process(shift_temp)
begin
if shift_temp='1' then temp_clk<=key_m;co<='0';
else temp_clk<=clk;co<=temp_co;
end if;
end process;
process(temp_clk)
begin
if temp_clk'event and temp_clk='1' then
if temp(3 downto 0)=9 then
if temp(7 downto 4)=5 then
temp<=(others=>'0');temp_co<='1';
else temp(7 downto 4)<=temp(7 downto 4)+1;temp(3 downto 0)<=(others=>'0');temp_co<='0';end if;
else temp(3 downto 0)<=temp(3 downto 0)+1;temp_co<='0';end if;
end if;
end process;
q<=temp;
end Behavioral;

******************************小时**********************************
entity count24 is
Port ( shift_temp,key_m,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0));
end count24;

architecture Behavioral of count24 is
signal temp_q:std_logic_vector(7 downto 0):=(others=>'0');
signal temp:std_logic_vector(4 downto 0);
signal temp_clk:std_logic;
begin
process(shift_temp)
begin
if shift_temp='1' then temp_clk<=key_m;
else temp_clk<=clk;
end if;
end process;
process(temp_clk)
begin
if temp_clk'event and temp_clk='1' then
if temp="10111" then temp<="00000";temp_q<=(others=>'0');
elsif temp="01001" or temp="10011" then
temp_q(3 downto 0)<="0000";temp_q(7 downto 4)<=temp_q(7 downto 4)+1;temp<=temp+1;
else temp_q(3 downto 0)<=temp_q(3 downto 0)+1;temp<=temp+1;
end if;
end if;
end process;
q<=temp_q;
end Behavioral;
************************分频****************************
entity clock is
Port ( clk : in STD_LOGIC;
clk_out:out std_logic_vector(3 downto 0));
end clock;

architecture Behavioral of clock is
signal temp_clk:std_logic_vector(3 downto 0);
signal temp0,temp1,temp2,temp3:std_logic_vector(24 downto 0):=(others=>'0');
begin
process(clk)
begin
if clk'event and clk='0' then
if temp0=24999999 then
temp_clk(0)<=not temp_clk(0);temp0<=(others=>'0');
else temp0<=temp0+1;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='0' then
if temp1=249999 then
temp_clk(1)<=not temp_clk(1);temp1<=(others=>'0');
else temp1<=temp1+1;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='0' then
if temp2=124999 then
temp_clk(2)<=not temp_clk(2);temp2<=(others=>'0');
else temp2<=temp2+1;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='0' then
if temp3=249 then
temp_clk(3)<=not temp_clk(3);temp3<=(others=>'0');
else temp3<=temp3+1;
end if;
end if;
end process;
clk_out<=temp_clk;
end Behavioral;
***********************调时闪烁**********************
entity clos is
Port (clk:in std_logic;
q : in STD_LOGIC_vector(2 downto 0);
q_out:out std_logic_vector(5 downto 0));
end clos;

architecture Behavioral of clos is
signal temp:std_logic_vector(5 downto 0);
begin
process(q)
begin
case q is
when "000"=>temp<=(others=>'0');
when "001"=>temp(0)<=clk;temp(1)<=clk;temp(5 downto 2)<="0000";
when "010"=>temp(3)<=clk;temp(2)<=clk;temp(5 downto 4)<="00";temp(1 downto 0)<="00";
when "100"=>temp(5)<=clk;temp(4)<=clk;temp(3 downto 0)<="0000";
when others=>null;
end case;
end process;
q_out<=temp;
end Behavioral;
*************************去抖动***********************************
entity kicker is
Port ( clk,din : in STD_LOGIC;
d_out:out std_logic);
end kicker;

architecture Behavioral of kicker is
signal x,y,d:std_logic:='0';
begin
process(clk)
begin
if clk'event and clk='1'
then x<=din;y<=x;d<=x and y;
end if;
end process;
d_out<=d;
end Behavioral;
******************调时控制信号************************
entity shift is
Port ( key_in : in STD_LOGIC;
shift_out: out std_logic_vector(3 downto 0));
end shift;

architecture Behavioral of shift is
signal data:std_logic_vector(3 downto 0):="0001";
begin
process(key_in)
begin
if key_in'event and key_in='1' then
data(2 downto 0)<=data(3 downto 1);
data(3)<=data(0);
end if;
end process;
shift_out(3 downto 0)<=data(3 downto 0);
end Behavioral;
*****************32位数据输出文件******************
entity count32 is
Port ( m,s,clk: in STD_LOGIC;
data:out std_logic_vector(31 downto 0);
close:out std_logic_vector(2 downto 0));
end count32;

architecture Behavioral of count32 is
component count100
Port ( shift_temp,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0);
co:out std_logic);
end component;
component count60
Port ( shift_temp,key_m,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0);
co:out std_logic);
end component;
component count24
Port ( shift_temp,key_m,clk: in STD_LOGIC;
q:out std_logic_vector(7 downto 0));
end component;
component kicker
Port ( clk,din : in STD_LOGIC;
d_out:out std_logic);
end component;
component shift
Port ( key_in : in STD_LOGIC;
shift_out: out std_logic_vector(3 downto 0));
end component;
component clock
Port ( clk : in STD_LOGIC;
clk_out:out std_logic_vector(3 downto 0));
end component;
signal temp:std_logic_vector(31 downto 0);
signal pinl:std_logic_vector(3 downto 0);
signal anjian:std_logic_vector(3 downto 0);
signal temp_co:std_logic_vector(2 downto 0);
signal qa,qc:std_logic;
begin
u1:count100 port map(anjian(0),pinl(1),temp(7 downto 0),temp_co(0));
u2:count60 port map(anjian(1),qa,temp_co(0),temp(15 downto 8),temp_co(1));
u3:count60 port map(anjian(2),qa,temp_co(1),temp(23 downto 16),temp_co(2));
u4:count24 port map(anjian(3),qa,temp_co(2),temp(31 downto 24));
u5:clock port map(clk,pinl);
u6:kicker port map(pinl(2),m,qa);
u7:kicker port map(pinl(2),s,qc);
u8:shift port map(qc,anjian);
data<=temp;close<=anjian(3 downto 1);
end Behavioral;
*********************8位数码管扫描**********************
entity weix is
Port ( clk : in STD_LOGIC;
close:in std_logic_vector(5 downto 0);
data : in STD_LOGIC_vector(31 downto 0);
bt : out STD_LOGIC_vector(7 downto 0);
sg: out STD_LOGIC_vector(7 downto 0));
end weix;

architecture Behavioral of weix is
signal cnt8:std_logic_vector(2 downto 0):="000";
signal temp:std_logic_vector(3 downto 0);
signal led7s:std_logic_vector(6 downto 0);
signal a:std_logic;
signal wei:std_logic_vector(7 downto 0):="11111110";
begin
process(cnt8)
begin
case cnt8 is
when"000"=>wei<="11111110";temp<=data(3 downto 0);a<='0';
when"001"=>wei<="11111101";temp<=data(7 downto 4);a<='0';
when"010"=> if close(0)='0' then wei<="11111011"; else wei<="11111111";end if;
temp<=data(11 downto 8);a<='1';
when"011"=> if close(1)='0' then wei<="11110111"; else wei<="11111111";end if;
temp<=data(15 downto 12);a<='0';
when"100"=> if close(2)='0' then wei<="11101111"; else wei<="11111111";end if;
temp<=data(19 downto 16);a<='1';
when"101"=> if close(3)='0' then wei<="11011111"; else wei<="11111111";end if;
temp<=data(23 downto 20);a<='0';
when"110"=> if close(4)='0' then wei<="10111111"; else wei<="11111111";end if;
temp<=data(27 downto 24);a<='1';
when"111"=> if close(5)='0' then wei<="01111111"; else wei<="11111111";end if;
temp<=data(31 downto 28);a<='0';
when others=>wei<= "11111111";
end case;
end process;
process(clk)
begin
if clk'event and clk='1'
then cnt8<=cnt8+1;
end if;
end process;
process(temp)
begin
case temp is
when "0000" => led7s<="0111111";
when "0001" => led7s<="0000110";
when "0010" => led7s<="1011011";
when "0011" => led7s<="1001111";
when "0100" => led7s<="1100110";
when "0101" => led7s<="1101101";
when "0110" => led7s<="1111101";
when "0111" => led7s<="0000111";
when "1000" => led7s<="1111111";
when "1001" => led7s<="1101111";
when others=>null;
end case;
end process;
sg(6 downto 0)<=led7s;sg(7)<=a;bt<=wei;
end Behavioral;
*******************电子时钟顶层文件****************
entity shizhong is
Port (oe:out std_logic_vector(2 downto 0);
er:out std_logic_vector(2 downto 0);
m,s,clk : in STD_LOGIC;
bt:out std_logic_vector(7 downto 0);
sg:out std_logic_vector(7 downto 0));
end shizhong;

architecture Behavioral of shizhong is
component count32
Port ( m,s,clk: in STD_LOGIC;
data:out std_logic_vector(31 downto 0);
close:out std_logic_vector(2 downto 0));
end component;
component clos
Port (clk:in std_logic;
q : in STD_LOGIC_vector(2 downto 0);
q_out:out std_logic_vector(5 downto 0));
end component;
component clock
Port ( clk : in STD_LOGIC;
clk_out:out std_logic_vector(3 downto 0));
end component;
component weix
Port ( clk : in STD_LOGIC;
close:in std_logic_vector(5 downto 0);
data : in STD_LOGIC_vector(31 downto 0);
bt : out STD_LOGIC_vector(7 downto 0);
sg: out STD_LOGIC_vector(7 downto 0));
end component;
signal temp:std_logic_vector(31 downto 0);
signal qa:std_logic_vector(2 downto 0);
signal qb:std_logic_vector(5 downto 0);
signal temp_clk:std_logic_vector(3 downto 0);
begin
u1:count32 port map(m,s,clk,temp,qa);
u2:weix port map(temp_clk(3),qb,temp,bt,sg);
u3:clock port map(clk,temp_clk);
u4:clos port map(temp_clk(0),qa,qb);
oe<="000";er<="110";
end Behavioral;

************索引脚******************
供参考
NET "bt<0>" LOC = "L21" ;
NET "bt<1>" LOC = "K22" ;
NET "bt<2>" LOC = "K21" ;
NET "bt<3>" LOC = "J22" ;
NET "bt<4>" LOC = "J21" ;
NET "bt<5>" LOC = "H22" ;
NET "bt<6>" LOC = "H21" ;
NET "bt<7>" LOC = "G22" ;
NET "clk" LOC = "A11" ;
NET "er<0>" LOC = "V20" ;
NET "er<1>" LOC = "F17" ;
NET "er<2>" LOC = "L18" ;
NET "m" LOC = "U21" ;
NET "oe<0>" LOC = "Y21" ;
NET "oe<1>" LOC = "L22" ;
NET "oe<2>" LOC = "M20" ;
NET "s" LOC = "T22" ;
NET "sg<0>" LOC = "R21" ;
NET "sg<1>" LOC = "R22" ;
NET "sg<2>" LOC = "P21" ;
NET "sg<3>" LOC = "P22" ;
NET "sg<4>" LOC = "N21" ;
NET "sg<5>" LOC = "N22" ;
NET "sg<6>" LOC = "M21" ;
NET "sg<7>" LOC = "M22" ;