在verilog中四输入引脚的与门在仿真时提示无信号源是为什么?

2024-11-30 01:52:05
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回答1:

integeri;integernumber_file;initialbeginnumber_file=$fopen("fir_threshold.txt","w");CLK=0;RST=0;#10RST=1;#20for(i=0;i<1000;i=i+1)begin#100$fwrite(number_file,"%d%d\n",i,$signed(your_data));end$fclose(number_file);end