VHDL设计的四位二进制加法计数器和减法计数器的代码？

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-----------------------------------------------
entity count is
port(
, clk: in std_logic;
K: in std_logic;
Q:buffer std_logic_vector(3 downto 0));
end count;
------------------------------------------------
architecture behave of count is
begin
process(clk)
variable temp:std_logic_vector (3 downto 0);
begin
if(clk'event and clk='1') then
if(K='0') then
temp:=temp+1;
else
temp:=temp-1;
end if;
end if;
q<=temp;
end process;
end behave;